// file: muxgate.v
// and/or gate level implementation of a mux
// C. Talarico

module mux (a, b, s, f4);
  input a, b, s;
  output f4;

  wire w_1,w_2,w_sb; //interconnecting wires

  // structural gate level modeling 
  nand U1(w_1,a,s);
  nand U2(w_2,b,w_sb);
  not U3(w_sb,s);
  nand U4(f4,w_1,w_2);

endmodule