// CPEN 230L lab 7 part 3, mux3w_5to1 and oct7seg complete circuit
// Firstname Lastname, mm/dd/yyyy

module muxdisp_top (
  input  [17:0] SW,      // 18 switches
  output [6:0] HEX0);    // 7-seg display

  wire [2:0] dispDrv_w;

  mux51_3bit mux_inst (//Write the inputs and outputs);

  displayDriver ddrvr_inst (// Write the inputs and outputs); 

endmodule