// CPEN 230L lab 9, JK Flip-Flop
// File: JK_FlipFlop.v

module JK_FlipFlop (
  input  nPr,    // asynchronous active-low preset
  input  nClr,   // asnychronous active-low clear
  input  Clk,    // positive edge triggered clock
  input  J,
  input  K,
  output reg Q,
  output Qn );

  wire Q_w;

  always @(posedge Clk, negedge nPr, negedge nClr) begin
    if (nClr == 1'b0) begin          // clear (has priority over preset)
      Q  <= 1'b0;
    end else if (nPr == 1'b0) begin  // preset
      Q  <= 1'b1;
    end else if ( J & ~K) begin      // set (nPr == 1 && nClr == 1)
      Q  <= 1'b1;
    end else if (~J &  K) begin      // reset
      Q  <= 1'b0;
    end else if ( J &  K) begin      // toggle
      Q  <= ~Q;
    end // else (~J & ~K), hold whatever value is stored in the FF
  end
  
  assign Q_w = Q;
  assign Qn = ~Q_w;

endmodule