// CPEN 230L lab 10, T Flip Flop
// File: T_FlipFlop.v

module T_FlipFlop (
  input      clk,       // positive edge triggered clock
  input      nReset,    // active low asynchronous reset
  input      T,         // Toggle input
  output reg Q);

  always @(posedge clk, negedge nReset)
    if (~nReset)
      Q <= 1'b0;
    else if (T)
      Q <= ~Q;

endmodule