// Testbench to illustrate the behavior of cascadeCounter 
// File: cascadeCounter.v 

`timescale 1ms / 100ns  // 1 sim tick = 1 ms, 100 ns resolution

module cascadeCounter_tb;
                        // DUT inputs and outputs
  reg        clk = 1;   // clock input to DUT
  reg        nRst;      // active low reset input to DUT
  wire [1:0] count0;    // DUT LSBs output
  wire [2:0] count1;    // DUT MSBs output

  // concatenate count1 and cout0 to observe the counting pattern
  wire [4:0] count;      
  assign count = {count1,count0};

  // We want 5 clock periods to correspond with 1 second, or 1/2 clock
  // period to correspond with 1/10 seconds = 100 ms = 100 simulation
  // time ticks.
  always
    #100 clk = ~clk;   // positive clock edges at 200, 400, 600... ms

  initial begin
    $dumpfile("cascadeCounter.vcd"); // for GTKWave
    $dumpvars(0, cascadeCounter_tb); // for GTKWave
    $display(" +----------------+");   // table header
    $display(" | cascadeCounter |");   // table header
    $display(" +----------------+");   // table header
    $display(" time  count");   // table header
    $monitor("%5d %6d",         // table formatting
      $time, count);            // table signals

                         // Test Procedure
           nRst = 1'b0;  // @t=0, reset
    #100   nRst = 1'b1;  // @t=100ms, 1st falling clock edge, count
    #12400 nRst = 1'b0;  // @t=12.5s, mid "2", stop counting
    #1500  $finish;      // @t=14s, finish
  end

  cascadeCounter DUT (  
    .clk    (clk),
    .nRst   (nRst),
    .count0 (count[1:0]),
    .count1 (count[4:2]));

endmodule