// CPEN 230L lab 10, general-purpose cascadable counter stage
// File: cntrStage.v

module cntrStage
  #(parameter cntr_bits_p = 4,      // number of bits in the counter
    parameter cntr_tc_p   = 9) (    // counter terminal count
  input  clk,                       // positive edge triggered clock
  input  nRst,                      // asynchronous active low reset
  input  enable,                    // synchronous active high enable
  output term_cnt,                  // set during terminal count
  output [cntr_bits_p-1:0] count ); // count value

  reg [cntr_bits_p-1:0] count_r;    // count register

  always @(posedge clk, negedge nRst) begin
    if (~nRst)
      count_r <= 0;              // if reset, set to 0
    else if (enable) begin
      if (count_r == cntr_tc_p)
        count_r <= 0;            // enabled & at TC, wrap to 0
      else
        count_r <= count_r + 1;  // enabled & not TC, increment
    end
  end

  // set outputs from registers used in the always block
  assign count = count_r;
  assign term_cnt = (count_r == cntr_tc_p);

endmodule