// file: mux.v
// four equivalent implementations of a mux
// C. Talarico

module mux (a, b, s, f1, f2, f3, f4);
  input a, b, s;
  output f1, f2, f3, f4;

  reg f3;
  wire w_1,w_2,w_sb; //interconnecting wires

  // implementation #1: 
  // cuncurrent modeling 
  assign f1 = (a & s) | (b & ~s);

  // implementation #2: 
  // cuncurrent modeling (higher abstraction level)
  assign f2 = (s) ? a : b; 
 
  // implementation #3:
  // always block modeling
  always @(*)
  begin
    if (s == 0) begin f3 <= b; end
    else begin f3 <= a; end //note: f3 must be a reg
  end

  // implementation #4
  // structural gate level modeling 
  nand U1(w_1,a,s);
  nand U2(w_2,b,w_sb);
  not U3(w_sb,s);
  nand U4(f4,w_1,w_2);

endmodule