-- 
-- author:   Claudio Talarico
-- file:     DFF_mux.vhd
-- comments: this code implements a muxed DFF 
--           (implementation #2)
--
library IEEE;
use IEEE.std_logic_1164.all;
 
entity DFF_mux is
  port ( 
    DIN : in std_logic;
    RST : in std_logic;
    CLK : in std_logic;
    EN  : in std_logic;
    DOUT: out std_logic);
end DFF_mux;

architecture RTL of DFF_muxed is
  signal Q : std_logic;
begin

   DFFmux_p : process(RST, CLK)
   begin
      if RST = '1' then
         Q <= '0';
      elsif CLK'event and CLK = '1' then
        if EN = '1' then
          Q <= DIN;
        end if;
      end if;
   end process DFFmux_p;

   -- dummy assignment
   DOUT <= Q;

end architecture RTL;