--
-- author:   Claudio Talarico
-- file:     DFF_muxed.vhd
-- comments: this code implements a muxed DFF
--           (implementation #1)
--

library IEEE;
use IEEE.std_logic_1164.all;
 
entity DFF_muxed is
  port ( 
    DIN : in std_logic;
    RST : in std_logic;
    CLK : in std_logic;
    EN  : in std_logic;
    DOUT: out std_logic);
end DFF_muxed;

architecture RTL of DFF_muxed is
  signal D : std_logic;
  signal Q : std_logic;
begin

   MUX_p : process(DIN, Q, EN)
   begin
     if EN = '1' then
       D <= DIN;
     else
       D <= Q;
     end if;
   end process MUX_p;

   DFF_p : process(RST, CLK)
   begin
      if RST = '1' then
         Q <= '0';
      elsif CLK'event and CLK = '1' then
         Q <= D;
      end if;
   end process DFF_p;

   -- dummy assignment
   DOUT <= Q;

end architecture RTL;