library IEEE;
use IEEE.std_logic_1164.all;
 
entity DFF_asy is
  port ( 
    D   : in std_logic;
    RST : in std_logic;
    CLK : in std_logic;
    Q   : out std_logic);
end DFF_asy;

architecture RTL of DFF_asy is
begin
   DFF_p : process(RST, CLK)
   begin
      if RST = '1' then
         Q <= '0';
      elsif CLK'event and CLK = '1' then
         Q <= D;
      end if;
   end process DFF_p;
end architecture RTL;