-- 
-- author:   Claudio Talarico
-- file:     ed-moore-so-rtl.vhd
-- comments: edge detector 
--           Moore FSM with stored output 
--

library ieee;
use ieee.std_logic_1164.all;

entity edge_detector is
port ( din   : in  std_logic;
       clk   : in  std_logic;
       rst_n : in  std_logic;
       dout  : out std_logic
     );

end edge_detector;

architecture rtl of edge_detector is

type state_t is (zero, posedge, negedge, one);
signal state, next_state : state_t;
signal next_pulse, pulse : std_logic;

------------------------------------------------------------------------
-- altera's specific attributes
attribute enum_encoding : string;
attribute enum_encoding of state_t : type is "sequential";
-- attribute enum_encoding of state_t : type is "gray";
-- attribute enum_encoding of state_t : type is "johnson";
-- attribute enum_encooding of state_t : type is "one-hot"; -- dafault
-- end of altera's specific attributes
------------------------------------------------------------------------

begin
 
  the_machine: process(din,state)
  begin

    -- defaults  
    next_state <= zero;
    next_pulse <= '0';

    case state is
      when zero => -- stable zero
        if (din = '0') then
          next_state <= zero;
          next_pulse <= '0';
        else
          next_state <= posedge;
          next_pulse <= '1';
        end if;
      when posedge => -- positive edge
        if (din = '0') then
          next_state <= negedge;
          next_pulse <= '1';
        else
          next_state <= one;
          next_pulse <= '0';
        end if;
      when negedge => -- negative edge 
        if (din = '0') then
          next_state <= zero;
          next_pulse <= '0';
        else
          next_state <= posedge;
          next_pulse <= '1';
        end if;
      when one => -- stable one
        if (din = '0') then
          next_state <= negedge;
          next_pulse <= '1';
        else
          next_state <= one;
          next_pulse <= '0';
        end if;
     when others =>
       -- do nothing
   end case; 

  end process the_machine;
    
  the_registers: process(clk, rst_n)
  begin
    if (rst_n = '0') then
      state <= zero;
      pulse <= '0';
    elsif (clk='1' and clk'event) then
      state <= next_state;
      pulse <= next_pulse;
    end if;
  end process the_registers;

  --dummy assignment
  dout <= pulse;

end rtl;