library  ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;   

entity memory is
port ( clk     : in std_logic;
       mread   : in std_logic;
       mwrite  : in std_logic;
       address : in std_logic_vector(6 downto 0);
       din     : in std_logic_vector(31 downto 0);
       dout    : out std_logic_vector(31 downto 0)
);
end memory;

architecture beh of memory is  		

  type mem_type is array (0 to 127) of std_logic_vector(31 downto 0);
  signal ram: mem_type;

begin
  						
memory: process(clk)
begin
  if (clk'event and clk = '1') then
    if (mwrite ='1' and mread = '0') then
      ram(conv_integer(address)) <= din;
    end if;
    if (mread ='1' and mwrite ='0') then
      dout <= ram(conv_integer(address));
    else
      dout <= (others => 'X');
    end if;
  end if;
end process;

end beh;