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-- 8-bit barrel shifter
-- Copyright 1995, Accolade Design Automation, Inc.
--
 
library ieee;
use ieee.std_logic_1164.all;
 
entity shifter is
 port( Clk, Rst, Load: in std_ulogic;
 Data: std_logic_vector(0 to 7);
 Q: out std_logic_vector(0 to 7);
 Qb: out std_logic_vector(0 to 7));
end shifter;
 
architecture rtl of shifter is
begin
  -- We use a process to describe the operation of
  -- the shifter over time, in response to its inputs...
  reg: process(Rst,Clk)
    -- Using a variable simplifies register feedback...
    variable Qreg: std_logic_vector(0 to 7);
    begin
      if Rst = '1' then -- Async reset
        Qreg := "00000000";
      elsif rising_edge(Clk) then
        if Load = '1' then
          Qreg := Data;
        else
          Qreg := Qreg(1 to 7) & Qreg(0);
        end if;
      end if;
      Q  <= Qreg;
      Qb <= not(Qreg);
  end process;
end rtl;