-- 
-- author:   Claudio Talarico
-- file:     timing.vhd
-- comment:  example to learn how to read timimg reports
--

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity timing is
port ( 
       clk       : in std_logic;
       sin       : in std_logic_vector(1 downto 0);
       sout      : out std_logic
     );
end timing ;

architecture rtl of timing is
  signal regi   : std_logic;
  signal rego   : std_logic;
  signal regi_d : std_logic;
  signal rego_d : std_logic;
begin
 
combo: process(sin,regi,rego)
variable a_v : std_logic;
variable b_v : std_logic;
begin
 a_v := sin(1) and sin(0);
 b_v := sin(1) xor sin(0);
 regi_d <= a_v;
 rego_d <= regi or a_v;
 sout   <= rego or b_v;
end process combo;
   
regs: process(clk)
begin
  if (clk='1' and clk'event) then
    regi<= regi_d;
    rego<= rego_d;
  end if;
end process regs;

end rtl;