-- 
-- author:   Claudio Talarico
-- file:     counter-rtl.vhd
-- comment:  up/down counter  by 10
--           the initial count (start_cnt) can be loaded
--

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.counter_pack.all;

entity counter is
port ( 
       up        : in std_logic; 
       ld        : in std_logic;
       start_cnt : in std_logic_vector(cnt_size_c-1 downto 0);
       ck        : in std_logic;
       rst       : in std_logic;
       cnt       : out std_logic_vector(cnt_size_c-1 downto 0) 
     );

end counter;

architecture rtl of counter is
  signal count_d  : unsigned(cnt_size_c-1 downto 0);
  signal count    : unsigned(cnt_size_c-1 downto 0);
begin
 
combinational_logic: process(start_cnt,count,ld,up)
begin

 if (ld = '1') then
   count_d <= unsigned(start_cnt);
  else
    if up = '1' then
      if (count = unsigned(final_cnt_c)) then
        count_d <= (others => '0');
      else
        count_d <= count + 1;
      end if;
    else
      if (count = unsigned(reset_cnt_c)) then 
        count_d <= unsigned(final_cnt_c);
      else
        count_d <= count - 1;
      end if;
    end  if;
 end if;

end process combinational_logic;
   
sequential_logic: process(ck, rst)
begin

  if (rst = '1') then
    count <= unsigned(reset_cnt_c);
  elsif (ck='1' and ck'event) then
    count <= count_d;
  end if;

end process sequential_logic;

--dummy assignment
cnt <= std_logic_vector(count);

end rtl;