CPEN 430: Course Topics

Quick Review of Digital Systems

• Combinational Logic, Sequential Logic, State Machines

• Timing Hazards

• Synchronous Digital Systems (RTL)

• Setup time, Hold time and Clock Skew

HDL Syntax and Structure (by examples)

HDL for Synthesis

System Design

• synthesis scripts

• synthesis reports

System Verification

• Testbenches and Functional Simulation

• Static Timing Analysis (STA)

Field Programmable Gate Arrays (FPGAs)

• FPGA's Fabric

• Design Flow and CAD Tools