CPEN 230L: Introduction to Digital Logic Lab

Fall 2017 - Claudio Talarico, Gonzaga University

Course Description

Number systems and codes, Boolean Algebra, Logic gates and flip-flops. Verilog HDL. Combinational and sequential Logic Design using CPLDs.

Schedule

Lab. S02: T 1:50 PM - 4:30 PM, HRK 214 and HRK 100

Office Hours:

M 10:00 AM - 12:00 PM
T,R 11:00 AM - 12:00 PM
Feel free to walk-in anytime or to make an appointment

Contact

Claudio Talarico
Professor, Electrical and Computer Engineering
Gonzaga University, 502 E. Boone Ave., Spokane, WA 99258
Office: HRK 215
Tel: (509) 313-3561
Fax: (509) 313-5871
email: talarico AT gonzaga DOT edu
www: http://web02.gonzaga.edu/faculty/talarico/

Announcements

No lab. the first week of class