CPEN 230L: Introduction to Digital Logic Lab

Spring 2018 - Claudio Talarico, Gonzaga University

Course Description

Number systems and codes, Boolean Algebra, Logic gates and flip-flops. Verilog HDL. Combinational and sequential Logic Design using FPGAs.

Schedule

Lab. S01: W 1:10 PM - 3:50 PM, HRK 214 and HRK 100

Office Hours:

  • T,R 11:00 AM - 12:00 PM

  • F 10:00 AM - 12:00 PM

  • Feel free to walk-in anytime or to make an appointment

Contact

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Claudio Talarico
Professor, Electrical and Computer Engineering
Gonzaga University, 502 E. Boone Ave., Spokane, WA 99258
Office: HRK 215
Tel: (509) 313-3561
Fax: (509) 313-5871
email: talarico AT gonzaga DOT edu
www: http://web02.gonzaga.edu/faculty/talarico/

Announcements

  • The first week lab. (T0) is in HRK 100

  • Next four week labs (L01-L04) are in HRK 214

  • All remaining labs are in HRK 100