EENG 406: Resources

Given the complexity of today's integrated circuits and systems the automation of the design process through computer-automated design (CAD) tools has become the only viable way to design chips.

This quarter the emphasis will be on the use of computer-aided design (CAD) tools to design Digital Application Specific Integrated Circuits (ASICs). The ultimate goal is to define a systematic set of procedures and CAD tools for the design of digital ASICs. The set of procedures and CAD tools that allows designers to progress from specification to final chip implementation is called Design Flow.

Linux

Most of the CAD tools we use run on Linux OS. The flavor of Linux we use is CentOS. Unless you are already familiar with Linux please read the following tutorials:

• Unix/Linux Quick Start

• Unix/Linux Summary

• Unix/Linux cheat sheet

If you plan to learn how to use the vim editor here are some resources:

• vim basics (this tutorial can be run interactively by typing the command vimtutor)

• The vim book by Steve Oualline

• A byte of vim by Swaroop C H

Shells Startup Files

• Sample .bashrc and .bash_profile files

Remote access to the CAD tools

• If you use MAC OSX or Linux OS open a terminal and ssh (secure shell) into the CAD server using ssh -CY yourusername@icl.gonzaga.edu

• If you use Windows OS download and install MobaXterm
  and ssh (secure shell) into the CAD server using ssh -CY yourusername@icl.gonzaga.edu

• If you need an sftp (secure file transfer protocol) application (on any platform) download fileZilla client

CAD Links

Schematic Entry

To enter our circuits we type the netlist with a text editor or use Galaxy Custom Designer Schematic Editor by Synopsys. Besides schematic capture Galaxy Custom Designer provides also a convenient Simulation and Analysis Environment (SAE).

If you are interested in a free tool providing schematic capture, circuit simulation and waveform viewer that works on Windows, MAC and Linux/Unix platforms I would encourage you to try LTSPICE by Linear Technology. To get started try the linked examples.
For more see:

• Tutorials and Examples by Jake Baker

• Tutorials and Examples by Terry Sturtevant

• Linear Technology's Blog

Circuit Simulation

To predict circuit behavior we use a CAD tool called SPICE (Simulation Program with Integrated Circuit Emphasis). The flavor of SPICE we use is called HSPICE. HSPICE is a commercial product widely used in industry and is provided by Synopsys. In order to see the results of our HSPICE simulations we have access to two Synopsys’ waveform viewers: CosmoScope and Custom Explorer.

HSPICE simulation results can be imported and post processed in MATLAB using the HSPICE toolbox for MATLAB developed by M. Perrott To refresh your SPICE skills please skim through the following HSPICE QuickStart tutorial. For more information please consult the extensive HSPICE documentation set.

HSPICE/MATLAB sample files:

• iv.sp

• plot_iv.m

Other resources you may find helpful:

• QuickStart Tutorial on using Galaxy Custom Design SE and SAE, Cosmoscope, HSPICE Toolbox for MATLAB

• UC Berkeley SPICE models (BSIM)

Technology

• MOSIS (Integrated Circuit Fabrication Service)

• MOSIS SCMOS (Scalable CMOS) Design Rules

• MOSIS/TSMC 180nm CMOS Logic Process (CL018)

• MOSIS SCMOS Design Kits

• MOSIS Digital Design Flow

• MOSIS SCMOS Design Flow

• Fabrication Schedule

• MOSIS FAQs

• MOSIS Search Engine

• TSMC 180nm Process Standard Cell Library Databook (by Artisan)

• TSMC 90nm Core Library Databook (GU students only)

• TSMC 90nm Standard I/O Library Databook (GU students only)

RTL Design and Synthesis

Register Transfer Level design is done using Synopsys VHDL Compiler.
Design synthesis is done using Synopsys Design Compiler and Synopsys Design Vision.

RTL Simulation

RTL simulation is done using Synopsys VCS-MX.

CAD Manuals and Databooks

The CAD Manuals and Databooks are accessible only to Gonzaga's students

VHDL

Language

• VHDL Language Guide (Accolade)

• Accellera System Initiative

Synthesis

• VHDL Guidelines for Synthesis (Siemens)

• Verilog Guidelines by Cliff Cummings

• VHDL Coding Guidelines for High Performances (Synopsys)

• Verilog Coding Guidelines for High Performances (Synopsys)

Coding Example (up/down counter)

• counter-pack.vhd

• counter-rtl.vhd

• tb_counter.vhd

• counter.log

• simulation waves

Design Flow

• VHDL Based Flow

Additional courses and web pages

• Jake Baker at UNLV

• David Harris at Harvey Mudd

• Bernard Boser at UC Berkeley

• Boris Murmann at Stanford

• Designer's Guide Community

• VLSI ans ASIC Technology Standrad Cell Library Design

• Predictive Technology Models at Arizona State University

• BSIM Modeling Group at UC Berkeley