EENG 406: Lectures

Lecture's slides are adapted from:

• N. Weste and D. Harris, “CMOS VLSI Design,” 4/e, Addison-Wesley

Class Notes are adapted from:

• N. Weste, K. Eshraghian, Principles of CMOS VLSI Design, 2/e, Addison-Wesley, 2000

• S. Kang, Y. Leblebici CMOS Digital Integrated Circuits, 3/e, McGraw-Hill, 2002

• J.P. Uyemura CMOS Logic Circuit Design, Kluwer Academic, 2003

• J. Rabaey, A. Chandrakasan, B. Nikolic Digital Integrated Circuits, 2/e, Prentice-Hall, 2002

Lectures

• Making of a Chip (by Infineon Technologies)

• Introduction to CMOS VLSI Design - Slide Set 1 - Technology Roadmap for Semiconductors

• Review of first and second order circuits

  • Ground Bounce Primer (EEtimes)

  • Understanding and Minimizing Ground Bounce (Fairchild Application Note)

  • Minimizing Ground Bounce & VCC Sag (ALTERA White paper)

  • High Speed Board Designs (Altera Application Note)

  • High Speed Board Design Techniques (AMD Application Note)

  • Printed Circuit Board Design Considerations (Xilinx Design Hints and Issues)

  • Grounding Essentials (Analog Devices Application Note)

• Circuit Simulation - Slide Set 2 (Basics of HSPICE)

• Linux: Quick Startup, Shell Scripts, Remote Access to the CAD Tools

• CMOS Digital Circuits - Slide Set 3

• CMOS Fabrication and Layout - Slide Set 4

• NAND3 layout example

• Examples of Stick Diagrams - Slide Set 5

• more stick diagrams examples

• MOS Transistor (ideal) - Slide Set 6

• MOS Transistor (non-ideal) - Slide Set 7

• MOS Transistor (SPICE LEVEL 1 models) - Slide Set 8

• MOS Transistor Modeling - Gm/ID design methodology (courtesy of R. Walker and B. Murmann)

• Max-delay Constraints, Min-delay Constraints, Clock Skew - Slide Set 9

• D flip flop Setup/Hold Time example

• Design for Reliability - ASIC Primer (LSI Logic) - Ch.3

• Design for Speed - ASIC Primer (LSI Logic) - Ch.4

• CMOS Inverter - Slide Set 10

• Interconnect - Slide Set 11

• Physics of PN and MOS structures

  • part i

  • part ii

  • part iii

  • part iv

• More on Gm/ID Methodology: Semiconductor Theory Background

• More on Gm/ID Methodology: Design Perspective

• ... more to come

Class Notes

• CMOS Technology

• MOS Transistors

• MOS as Switches

• Pass Transistors and Transmission Gates

• CMOS Inverter: DC Analysis

• CMOS Inverter: Transient Analysis

• CMOS Inverter: Power Dissipation

• Digital Systems: Quick Review

• CMOS Combinational Logic

• CMOS Sequential Logic

• Cgs of MOS transistor in Saturation

Learning Objectives:

• Analyze and design basic logic circuits that form the building blocks of a digital integrated system particularly with applications to combinational logic gates and sequential logic gates

• Evaluate the chip area required to layout different logic circuits

• Use circuit simulation (SPICE) to verify the functionality of basic logic circuits

• Use circuit simulation (SPICE) to analyze and improve the performance metrics of basic logic circuits

• Explain Layout Design Rules for CMOS Processing Technology

• Model and estimate the propagation delay of CMOS gates

• Explain the role of design margin and reliability

• Use various CAD tools (design entry, synthesis, static timing analysis, simulation, verification and layout)