CPEN 430: Schedule

Fall 2016 - Claudio Talarico, Gonzaga University

Lectures	Links
Review of Digital Systems	Altera's Primitive Lists Designing with Low-Level Primitives
MUX 2:1 example mux-rtl.vhd mux-tb.vhd Designing Reliable Digital Systems
Altera's Design Flow FPGA's Fabric HDLs Motivation Structural VHDL	Cyclone IV Handbook shifter.vhd compare.vhd shiftcomp.vhd
VHDL Coding by Example: Code Structure Data Types Operators and Attributes Concurrent Coding vs. Sequential Coding Objects to hold Data	dff_asy.vhd dff_syn.vhd count.vhd DFF_muxed.vhd (Implementation #1) DFF_mux.vhd (Implementation #2)
`Oct. 11`	`Exam #1`
VHDL Coding of State Machines: State Machines ASM charts
Design Example: Edge Detector Edge Detector Simulation	ed-mealy-rtl.vhd ed-moore-rtl.vhd ed-moore-so-rtl.vhd tb-ed.vhd
VHDL for Synthesis
VHDL Coding Guidelines	VHDL Coding for High Performance
VHDL Testbenches by Example: Delay Models Packages and Components Generics Generate Functions and Procedures
Files	UpDown Counter: counter-pack.vhd counter-rtl.vhd tb_counter.vhd (counter.log) (simulation waves)
	Sync. Memory (beh. model): memory-beh.vhd tb_memory.vhd memory.vec memory.TBF
Constraining a Design for Synthesis Synthesis Overview Synthesis Process Design Objects Synthesis Partitioning
Timimg Constraints Environmental Attributes Timing Reports	Quartus Timequest (Static Timing Analysis) Quartus STA Quick Start Tutorial Quartus Timequest User Guide (by Ryan Scoville) Quartus Timequest STA Cookbook SDC and TimeQuest API Reference Manual Quartus II Handbook, vol.3, Ch.7 Example: timing.vhd - timing.sdc - timing.tcl
ASIC Design Guidelines (LSI Logic)
`Nov. 15`	`Exam #2`
`Wednesday, Nov. 23 - Friday, Nov. 25`	`Thanksgiving Holiday`
Metastability	Ginosar, Metastability and Synchronizers - A tutorial Ginosar, 14 Ways to fool your synchronizer
	Guest Lecture: Justin Wagner (Ciena) Hani Lashgari (Ciena) Adam Huson (F5 Networks)
`Dec. 1`	`Exam 3`

Learning Objectives:

Demonstrate proficiency coding in HDL (Hardware Decription Language).
Design basic functional units with HDL.
Design advanced application specific function units with HDL.
Demonstrate how to map a design described in HDL into FPGA (Field Programmable Gate Array)
Apply HDL to various application problems